Side by Side: The Interposer Approach

The most widely deployed advanced-packaging approach for AI accelerators places the logic die and its memory stacks next to each other on a shared silicon interposer. Think of the interposer as a small, passive floor made of the same material as the chips, whose entire purpose is dense horizontal wiring. The dies sit on this floor side by side, and the floor carries the enormous number of connections between them. Because the wiring is chip-grade rather than board-grade, it can be far finer than any substrate, which is exactly what the memory bandwidth demands.

The reason this approach became the default for high-end accelerators is memory. High-bandwidth memory works by exposing an extraordinarily wide interface, thousands of connections per stack, rather than a fast-but-narrow one. To use that width you need a routing layer that can physically fan out thousands of wires between the logic die and each stack across a very short distance. A silicon interposer does this; an organic substrate alone cannot. So the side-by-side-on-interposer construction and high-bandwidth memory grew up together, each making the other viable.

The cost is capacity of a specific kind. The interposer itself is fabricated on semiconductor tooling, often larger than a normal chip because it must span the logic die plus all its memory stacks. As accelerators add memory, the interposer grows, and larger interposers are harder to make at good yield and consume more of the line per unit. There is a ceiling on how large a single interposer can be, tied to the size of the fields the lithography tools can print, and pushing against that ceiling is one of the recurring engineering fights of each generation. Designs that need more memory than a standard interposer can host must resort to schemes that stitch or extend the routing area, which add their own complexity and cost.

This is the approach most people mean when they say advanced packaging is the bottleneck. The line that builds these interposer assemblies is the one the dominant foundry has repeatedly described as sold out. Its capacity is measured in a rate of finished assemblies per month, and that rate has trailed demand for successive accelerator generations. Because the interposer scales with memory content, and because each accelerator generation tends to carry more memory, the capacity consumed per unit rises even if the number of units does not, tightening the constraint from two directions at once.

There is also a variant worth understanding: instead of a full silicon interposer spanning everything, some designs use localized silicon bridges, small pieces of dense silicon embedded in the substrate only where two dies need to talk, with ordinary substrate wiring everywhere else. This trades some routing density for lower cost and better scalability, since you are not fabricating one enormous interposer. The bridge approach and the full-interposer approach coexist, and which one a design uses affects which supplier and which facility its production depends on. From a supply standpoint the lesson is that side-by-side is not one thing but a family, and the family members lean on different capacity.

It is worth pausing on why the interposer, a passive slab with no transistors doing useful work, became the scarce thing at all. Intuition says the hard part must be the logic die, the piece packed with billions of switches. But the logic die rides a mature, heavily built-out process, while the large interposer and the assembly step that mounts dies onto it at sub-micron alignment are comparatively young at this scale. Scarcity in manufacturing does not track sophistication; it tracks how much capacity was built before demand arrived. The interposer line was small when accelerator demand exploded, and passive though the part is, the line that makes and populates it is the gate.

The takeaway for reasoning about supply is concrete. When you read that an accelerator uses a certain amount of high-bandwidth memory, you can infer something about the interposer it needs, and therefore something about the packaging capacity it consumes. More memory means a larger integration area, which means more of a scarce line per unit and a tighter squeeze on the facilities that build these assemblies. The visible spec at the top, memory capacity, is a readable proxy for the invisible constraint underneath, packaging area. Learning to make that inference is most of what separates someone who can forecast accelerator supply from someone who merely quotes wafer numbers, and it is why the side-by-side interposer sits at the center of every serious capacity discussion.