The Second Bottleneck: Why Wafers Were Never the Whole Story
For a decade the industry told a simple story: chip supply equals wafer supply. Build more fabs, print more silicon, ship more accelerators. That story is now wrong, and the people running the largest compute build-outs on earth learned it the hard way. A finished accelerator is not a die. It is a die married to memory stacks, sitting on an interposer, mounted on a substrate, inside a package that itself must be manufactured on a separate line with its own tools, its own yield curve, and its own multi-year lead time. When that line is full, more wafers do nothing. Faraday's read: the binding constraint moved downstream, and most forecasts have not caught up.
Knowledge check
Why does adding wafer fabrication capacity fail to increase accelerator supply when advanced packaging is the bottleneck?
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Because a finished accelerator requires the die to be integrated with high-bandwidth memory on an interposer and substrate through a separate advanced-packaging line. If that packaging line is saturated, additional bare dies simply queue behind it; they cannot become shippable products until they pass through packaging, so wafer output rises while shippable-unit output does not.