Losses, PUE, and the Grid That Shapes It All

Now account for the whole journey. A watt entering at the substation does not arrive whole at the transistor. It is taxed a little at every transformation and every conductor: a fraction of a percent at the step-down transformer, a bit more across the medium-voltage campus, a few percent through the UPS, more at the building transformer and the PDUs, several percent at the server power supply, and again at the voltage regulator beside the chip. Each stage is efficient in isolation — often well above 95 percent — but efficiencies multiply, and a long chain of high-nineties stages still compounds into a meaningful total loss between the fence and the silicon.

The industry's summary metric for this is power usage effectiveness, or PUE: the ratio of total facility power to the power actually delivered to the IT equipment. A PUE of 2.0, common a decade ago, meant that for every watt reaching a server, another full watt was consumed by cooling, power conversion losses, and lighting. Modern hyperscale designs push PUE toward 1.1 or below, meaning overhead has been squeezed to a small fraction of the IT load. Crucially, PUE captures the cost of moving and conditioning power and the cost of removing the heat that power becomes — and every conversion loss described in this course shows up twice: once as wasted input power, and again as heat the cooling system must then reject.

That double penalty is why the efficiency of the power stack matters more than it first appears. A percentage point lost in the UPS or the server power supply is not just a percentage point of input power wasted — it is also a percentage point of heat added to the thermal load, which the cooling system must spend still more power to remove. Efficiency in the power path pays twice. This is the economic engine behind every trend in the stack: higher distribution voltages to cut resistive loss, more efficient UPS modes that bypass conversion when the grid is clean, higher-efficiency power supplies, and 48-volt boards that shrink the biggest currents. Each is an attack on a loss that would otherwise be paid for twice.

Step back to the full trace and the system reveals its unity. The same physical law — resistive loss scales with the square of current — drives the design at every scale. It is why the grid transmits at hundreds of kilovolts, why the campus distributes at medium voltage, why the building buffers and splits at low voltage, and why the board is moving to 48 volts before the final plunge to the chip. Keep voltage high and current low across every span of distance; step down only at each boundary where the power must be used; and press the final, highest-current conversion as close to the load as physics allows. From the transmission tower to the transistor, it is one strategy applied recursively.

And the loop closes at the gate. The grid connection secured at the point of interconnection set the firm megawatts the site can draw — the hard ceiling on total power. Everything downstream is the engineering of spending that budget well: how much of it survives the conversions to reach the chips, how much is lost as heat, and how much extra must be spent to remove that heat. A site with a 300-megawatt firm interconnection and a PUE near 1.1 delivers far more compute than a site with the same interconnection and a PUE of 1.5, because the second site is burning a third of its scarce, years-in-the-making grid capacity on overhead. The interconnection sets the size of the pie; the power stack determines how much of it becomes computation.

This is why the grid connection shapes every downstream choice. The voltage at the gate sets how many transformation stages the site must build. The firm capacity sets how much redundancy the site can afford to power. The energization date, governed by a transformer's multi-year lead time, sets when any of it can earn revenue. And the efficiency of the entire stack determines how much of that hard-won, grid-limited power actually reaches silicon rather than being lost and then cooled away. The gate is not the beginning of the system and the chip its end. They are two ends of one continuous power path, and a decision at either end ripples through the whole.

So trace the watt one more time, and hold the whole picture at once. It leaves the transmission line at a voltage that can jump across air, steps down at a substation built around a transformer that took years to deliver, crosses the campus at medium voltage along redundant paths, enters the building and is buffered by stored energy so the grid can blink without the chips noticing, is split thousands of ways down to the rack, and finally collapses to a single volt in the last few millimeters beside the processor, where the current is so vast it can only be converted on the spot. One unit of electricity, one continuous system — and to understand its whole path, from the grid connection to the chip, is to understand the entire power stack as the single machine it truly is.